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OTIS1.0

Layout of the OTIS 1.0 Chip
This is the full-size prototype of the OTIS chip. Besides the final number 32channels, it also implelements the full amounts of pipeline and derandomizer buffer memory. Further features already implemented are the I2C interface controlling the chip setup as well as the DACs for ASD threshold adjustment. Also the programmable hit scanning in up to 3 samples (or bunch crossings) is already implemented. However, since the chip is a prototype, it has some limitations:
Only the "single hit- encoded drift time" readout mode is implemented. It is described in the following table:

Header
data CH0
......
data CH31
32 bits
8 bit
......
8 bit


The Channel data is coded as follows, since only the first hit per channel is transmitted:
Hit position data
1. Sample 00xxxxxx
2.Sample 01xxxxxx
3. Sample 10xxxxxx
no hit 11xxxxxx

xxxxxx indicates the 6bit fine time.
   
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Last change: 15 Oct 2002