OTISDLL

OTISDLL is the first chip submitted by us for this project. From the fact that it even has no version number you may guess that we did not trust it too much ;-). Anyhow, it is our first chip that is up and running. Below, you can find information on it.

Specification

OTISDLL is a chip of 2 x 2 mm size implemented in the 0.25um CMOS process we intend to use for the whole project.

It implements a standard DLL containing of

• a delay chain made of 32 pairs of starved inverters, into which an external reference clock is fed,
• a phase detector which compares the phase of the external reference with the output of the delayed clock
• a charge pump
• and a loop filter

Since we will operate at the LHC bunch crossing clock of 40MHz, our DLL should have an intrinsic resolution of 25ns/32 = 780ps. That just fits the spec of below 1ns.

Measurements

Up to now we have only tested a single OTISDLL chip. The results can be summarized as follows.

Power consumption

5.8mA at 2.5V power supply, i. e. 14.5mW power consumption

Lock range

The lock range is 22MHz...44MHz. This is lower than intended (30MHZ..50MHz, 40MHz in the middle of this interval). This is understood and already corrected for the next release of the DLL.

Lock time

Lock time is well below 2us, as can be seen in the following picture.

Integral Linearity

Not yet measured.

Differential Linearity

The DNL at 40MHz is 1.9 corresponding to 1.482ns.
The DNL at 30MHz is 0.58 corresponding to 0.604ns.

The Differential Non-Linearity (DNL) was measured by sampling about 30.000 pulses that were generated with an oscillator running asynchronously to the 40MHz sampling clock of the DLL. Hence the pulses arrive randomly distributed within a clock time interval. The mean number of hits per bin is about 1000, which gives a statistical error of 3%. Building the difference between neighbours and scaling by the mean number of events per bin results in the histograms shown below. The DNL is the width of the histograms' envelope.

As can be seen, the maximum deviation from the optimum shows up at the first time bins. This is partly due to the fact that switching of the charge pump occurs at this time (in bins 3 to 4) but the main effect is the first bin. The reason is a dummy delay element at the front of the delay chain that is not regulated and which has a wrongly dimensioned size (it is optimum for 30MHz clock). For illustration the DNL for 30MHz, which is the optimum for the first delay element, is also shown in a second histogram. Here, the deviation of the first bin does not domnate the DNL any longer.